1. Field of the Invention
The present invention relates to methods of making a semiconductor device (hereinafter xe2x80x9cLSI devicexe2x80x9d).
2. Description of the Related Art
An LSI device has many technical requirements such as high-speeds, low power consumption, versatile functions, and high integration degrees, and it is necessary to develop a circuit pattern which has no less functions and/or better electrical characteristics at a smaller occupied area than those of the current LSI devices.
In the process for making LSI devices, a number of treatments or photolithographic techniques (hereinafter xe2x80x9clithographic techniquesxe2x80x9d) are applied to the surface of a semiconductor silicon wafer (hereinafter xe2x80x9cwaferxe2x80x9d) to form a microscopic circuit pattern thereon.
A photoresist pattern corresponding to the circuit pattern formed by lithographic technique is used as a masking material to perform etching a thin film material or injecting an impurity ion. By repeating such treatments for a number of times, a desired LSI circuit pattern is formed.
However, the resolution with which the microscopic circuit pattern is formed in the lithographic technique and the circuit pattern is positioned on the layer is approaching the limit. Consequently, the formed photoresist pattern fails to meet the required working precision for the LSI circuit pattern.
In FIGS. 2(a) and 3(a), a silicon monocrystal substrate (hereinafter xe2x80x9csilicon substratexe2x80x9d) is indicated by reference numeral 21. A field oxide (SiO2) film 22 having a thickness of 2000-8000 xc3x85 is formed by the well known LOCOS process. A channel stopper or impurity diffusion region (not shown) is provided in the silicon substrate 21 to form an electrical insulation region.
An electrode pattern 23 is made from a polycrystal silicon (hereinafter xe2x80x9cpolysiliconxe2x80x9d) having a thickness of 1000-4000 xc3x85 or a film containing a metal of high melting point, such as tungsten, molybdenum, or titanium, or a eutectic film of silicon and a metal having a high melting point. A thin silicon oxide film (not shown) having a thickness of 50-500 xc3x85 is made under the electrode pattern 23.
An interlayer insulation or oxide film 24 having a thickness of 1000-8000 xc3x85 is formed. A photoresist film 25 is formed by the lithographic technique to provide a photoresist pattern 26. The photoresist film 25 is used as a mask to etch a contact pattern or hole 26xe2x80x2 in the interlayer insulation film 24.
Problems arising from the fact that the lithographic technique reaches its precision limit will be described with reference to FIGS. 2(b)-(d) and 3(b)-(d).
In FIGS. 2(b) and 3(b), the photoresist pattern 26a formed by the lithographic technique is slightly offset from the underground pattern to make contact with the electrode pattern 23.
Consequently, a portion of the contact pattern 26axe2x80x2 is formed on the edge of the electrode pattern 23. As a result, a wiring material formed within the contact pattern 26axe2x80x2 makes contact with the electrode pattern 23 as shown by A in FIG. 3(b), providing a electrical circuit failure or defect LSI device.
This problem results from the fact that the photoresist pattern 26a is formed at a slightly offset position by the lithographic technique. This problem has been negligible in making LSI devices having a circuit pattern dimension of 0.5 xcexcm or more. However, this problem is no longer negligible for a circuit pattern dimension of 0.4 xcexcm or less.
In FIGS. 2(c) and 3(c), the contact pattern 26 is slightly offset in the direction opposite to that of FIGS. 2(b) and 3(b). The contact pattern 26b formed on the photoresist film 25 is offset from the electrode pattern 23 and laid on the edge of the field oxide film 22. Consequently, the contact pattern 26bxe2x80x2 formed in the interlayer insulation film 24 cuts a portion of the field oxide film 22 as shown by B in FIG. 3(c). As a result, a portion of the channel stopper (not shown) formed under the field oxide film 22 is exposed.
When a wiring material is formed, the exposed portion is prone to an electrical leak to the silicon substrate 21, providing a defective LSI device.
In FIGS. 2(d) and 3(d), the contact pattern 26c formed on the photoresist film 25 is larger than the designed pattern.
Similarly to the problems in FIGS. 2(b), 2(c), 3(b), and 3(c), the wiring material formed within the contact pattern 26cxe2x80x2 makes connection with the electrode pattern 23 as shown by C in FIG. 3(d) or allows an electrical leak from the field oxide film 22 to the silicon substrate 21 as shown by Cxe2x80x2 in FIG. 3(d).
In addition, the precision problem, such as the too large contact pattern 26cxe2x80x2, reduces the tolerance for positioning offset so that the yield of LSI devices is reduced by both of the factors of positioning and dimension precision. A number of measures for minimizing these disadvantages have been proposed.
A representative example will be described with reference to FIGS. 4(a)-(d).
In FIG. 4(a), reference numeral 21 denotes a semiconductor substrate, 24 an interlayer insulation film, 25 a photoresist film, 26 a photoresist pattern formed in the photoresist film 25, and 26xe2x80x2 a contact pattern formed in the interlayer insulation film 24.
A substrate portion 21xe2x80x2 is exposed by etching the interlayer insulation film 24, and its surface is slightly damaged by the etching process. This damage is omitted in FIGS. 2(a)-(d) and 3(a)-(d).
In FIG. 4(b), the photoresist film 25 is removed.
In FIG. 4(c), an insulation film material or silicon oxide film 41 is formed on the interlayer insulation film 24 and within the contact pattern 26xe2x80x2 by the chemical vapor deposition (CVD) process to a thickness of 600-4000 xc3x85.
In FIG. 4(d), an anisotropic etching process is applied to the entire surface of the oxide film 41 to proceed in the perpendicular direction (hereinafter xe2x80x9cetchback processxe2x80x9d). Consequently, only the oxide films 41xe2x80x2 on the side walls of the contact pattern 26xe2x80x2 remain.
Consequently, the diameter of the contact pattern or hole 26xe2x80x2 is reduced by the side wall oxide films 41xe2x80x2 to thereby minimize the above problems in FIGS. 2 and 3. In this method, however, the silicon substrate portion 21xe2x80x3 is exposed again upon formation of the side wall oxide film 41xe2x80x2 so that the etching damage is accumulated.
In addition, the thickness of the side wall oxide film 41xe2x80x2 is determined by the thickness of the oxide film 41 formed by the CVD process, which in return determines the effective size of the final contact pattern 26xe2x80x2. Consequently, in order to minimize the problems of FIGS. 2 and 3 by reducing the size of the contact pattern 26xe2x80x2, it is desired to form a thick oxide film 41 by the CVD process.
However, the contact pattern 26xe2x80x2 itself is very small and can be formed too small to provide satisfactory etchback process as shown at 27 in FIG. 5(a) owing to the precision problem of the lithographic technique. Consequently, a defective opening 41xe2x80x3 of the contact pattern 27 can be made as shown in FIG. 5(b).
The defective opening 27 can also result from variations in the thickness of the oxide film 41 formed by the CVD process, leading to a defective LSI device.
If the etchback process is increased to reduce the frequency that the defective opening of the contact pattern 27 is produced, the damage to the substrate portion 21xe2x80x3 exposed by the etching process in FIG. 4(d) increases.
The damage, which appeared to be caused by impurities injected in the etching process or crystal defect produced in the silicon substrate 21, increases variations in the electrical resistance at the contact or increases the electrical resistance. Such variations in the electrical resistance are no longer negligible for submicron technology.
In order to reduce the number of defective openings of the contact pattern and variations in the electrical resistance at the contact area, it is necessary to reduce the thickness of the oxide film 41 formed by the CVD process. However, such reduction of the oxide film 41 is disadvantageous for solving the problems of FIGS. 2 and 3.
That is, the measure of FIG. 4(d) is not fully satisfactory, and there is a need for further improvement.
Accordingly, it is an object of the invention to provide a method of making a semiconductor device, which is capable of minimizing the etching dimension of a contact pattern formed in an insulation film without changing the lithographic technique.
According to the invention there is provided a method of making a semiconductor device, comprising the steps of etching, with a resist pattern used as a mask, a contact pattern in at least one interlayer insulation film made on a silicon substrate; forming on the contact pattern an insulating film containing silicon as a main component; and oxidizing by heat treatment the insulation film to form an oxide film including a side wall oxide film on an inside wall of the contact pattern.
According to an embodiment of the invention, the etching step is made such that the etching pattern does not reach the silicon substrate.
According to another embodiment of the invention, the etching step makes use of a difference in etching speed between the interlayer insulation films.
According to still another embodiment of the invention, the interlayer insulation films are a nitride film and an interlayer oxide film beneath the nitride film, with the contact pattern formed in the nitride film, and the method further comprising the step of applying, subsequent to formation of the side wall oxide films, a blanket etchback process to simultaneously etch the interlayer oxide film.
According to yet another embodiment of the invention, the interlayer insulation films are an oxide film and a nitride film beneath the oxide film, with the contact pattern formed in the oxide film, and the method further comprising the step of applying, subsequent to formation of the side wall oxide films, a blanket etchback process, followed by etching the nitride film.
According to another embodiment of the invention, the interlayer insulation films are a first interlayer oxide film, a nitride film, and a second interlayer oxide film, with the contact pattern formed in the first oxide film, and the method further comprising the step of applying, subsequent to formation of the side wall oxide film, a blanket etchback process, followed by etching the nitride and second interlayer oxide films.
According to still another embodiment of the invention, the interlayer insulation films are a first interlayer oxide film, a nitride film, and a second interlayer oxide film, with the contact pattern formed in the first oxide and nitride films, the method further comprising the step of applying, subsequent to formation of the side wall oxide film, a blanket etchback process to simultaneously etch the second interlayer oxide film.